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NB7L1008M 2.5V / 3.3V 1:8 CML Fanout
Multi-Level Inputs w/ Internal Termination
Description http://onsemi.com MARKING
32 DIAGRAM 1
The NB7L1008M is a high performance differential 1:8 Clock/Data fanout buffer. The NB7L1008M produces eight identical output copies of Clock or Data operating up to 6 GHz or 10.7 Gb/s, respectively. As such, the NB7L1008M is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. This feature allows the NB7L1008M to accept various logic standards, such as LVPECL, CML, LVDS, LVCMOS or LVTTL logic levels. The VREFAC reference output can be used to rebias capacitor-coupled differential or single-ended input signals. The 1:8 fanout design was optimized for low output skew applications. The NB7L1008M is a member of the GigaCommTM family of high performance clock products.
Features
1
32
QFN32 MN SUFFIX CASE 488AM A WL YY WW G
NB7L 1008M AWLYYWWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location)
* * * * * * * * * * * * * * *
Input Data Rate > 12 Gb/s Typical Data Dependent Jitter < 20 ps Maximum Input Clock Frequency > 8 GHz Typical Random Clock Jitter < 0.8 ps RMS Low Skew 1:8 CML Outputs, < 25 ps max Multi-Level Inputs, accepts LVPECL, CML, LVDS 160 ps Typical Propagation Delay 45 ps Typical Rise and Fall Times Differential CML Outputs, 400 mV Peak-to-Peak, Typical Operating Range: VCC = 2.375 V to 3.6 V, GND = 0 V Internal Input Termination Resistors, 50 W VREFAC Reference Output QFN-32 Package, 5 mm x 5 mm -40C to +85C Ambient Operating Temperature These are Pb-Free Devices
SIMPLIFIED LOGIC DIAGRAM
Q0 Q0
Q1 Q1
Q2 Q2
IN VT 50W 50W IN VREFAC
Q3 Q3
Q4 Q4
Q5 Q5
Q6 Q6
Q7 Q7
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2008
December, 2008 - Rev. 0
1
Publication Order Number: NB7L1008M/D
NB7L1008M
Exposed Pad (EP)
VCC
Q0
32 VCC GND IN VT VREFAC IN GND VCC 1 2 3 4 5 6 7 8 9 VCC
31
Q0
30
29
28
27
26
25 24 23 22 21 GND VCC Q3 Q3 Q4 Q4 VCC
NB7L1008M
VCC
Q1
Q1
Q2
Q2
20 19 18 17
GND
10 Q7
11 Q7
12 Q6
13 Q6
14 Q5
15 Q5
16 VCC
Figure 1. 32-Lead QFN Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin 3, 6 4 2, 7 17,24 1, 8, 9, 16, 18, 23, 25, 32 31, 30, 29, 28, 27, 26, 22, 21, 20, 19, 15, 14, 13, 12, 11, 10 5 - Name IN, IN VT GND VCC Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4, Q5, Q5, Q6, Q6, Q7, Q7 VREFAC EP - CML I/O LVPECL, CML, LVDS Input Description Non-inverted / Inverted Differential Clock/Data Input. Note 1 Internal 50 W Termination Pin for IN and IN Negative Supply Voltage, Note 2 Positive Supply Voltage, Note 2 Non-inverted / Inverted Differential Output. Note 1
Output Voltage Reference for Capacitor-Coupled Inputs, only The Exposed Pad (EP) on the QFN-24 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is electrically connected to GND and is recommended to be electrically connected to GND on the PC board.
1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal is applied on IN/IN, then the device will be susceptible to self-oscillation. Qn/Qn outputs have internal 50 W source termination resistors. 2. All VCC and GND pins must be externally connected to the same power supply voltage to guarantee proper device operation.
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NB7L1008M
Table 2. ATTRIBUTES
Characteristics ESD Protection Human Body Model Machine Model Value > 2 kV > 200 V Level 1 UL 94 V-0 @ 0.125 in 263
Moisture Sensitivity (Note 3) Indefinite Time of the Drypack QFN-32 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, refer to Application Note AND8003/D. Oxygen Index: 28 to 34
Table 3. MAXIMUM RATINGS
Symbol VCC VIN VINPP IIN Iout IVFREFAC TA Tstg qJA qJC Tsol Positive Power Supply Input Voltage Differential Input Voltage |IN - IN| Input Current Through RT (50 W Resistor) Output Current VREFAC Sink/Source Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 4) TGSD 51-6 (2S2P Multilayer Test Board) with Filled Thermal Vias Thermal Resistance (Junction-to-Case) Wave Solder Pb-Free 0 lfpm 500 lfpm Standard Board QFN-32 QFN-32 QFN-32 Continuous Surge Parameter Condition 1 GND = 0 V GND = 0 V Condition 2 Rating 4.0 -0.5 to VCC 1.89 $40 34 40 $1.5 -40 to +85 -65 to +150 31 27 12 265 Unit V V V mA mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7L1008M
Table 4. DC CHARACTERISTICS - CML OUTPUT VCC = 2.375 V to 3.6 V; GND = 0V TA = -40C to 85C (Note 6)
Symbol POWER SUPPLY VCC Power Supply Voltage VCC = 3.3 V VCC = 2.5 V 3.0 2.375 3.3 2.5 3.6 2.625 V Characteristic Min Typ Max Unit
POWER SUPPLY CURRENT ICC VOH Power Supply Current, Inputs and Outputs Open 265 315 mA
CML OUTPUTS (Note 5, Figures 10 and 11) Output HIGH Voltage VCC = 3.3V VCC = 2.5V VCC = 3.3V VCC = 2.5V VCC - 30 3270 2470 VCC - 600 2700 1900 VCC - 10 3290 2490 VCC - 400 2900 2100 VCC 3300 2500 VCC - 350 2950 2150 mV
VOL
Output LOW Voltage
mV
DIFFERENTIAL INPUTS DRIVEN SINGLE-ENDED (Notes 7 and 8) (Figures 6 and 8) VIH VIL Vth VISE VREFAC VREFAC Output Reference Voltage @ 100 mA for Capacitor - Coupled Inputs, Only VCC = 3.3 V VCC = 2.5 V VCC - 1375 VCC - 1325 VCC - 1200 VCC - 1200 VCC - 1100 VCC - 1075 mV Single-Ended Input HIGH Voltage Single-Ended Input LOW Voltage Input Threshold Reference Voltage Range Single-Ended Input Voltage (VIH - VIL) Vth + 100 GND 1100 200 VCC Vth - 100 VCC - 100 1200 mV mV mV mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (IN, IN) (Note 9) (Figures 4 and 7) VIHD VILD VID IIH IIL RTIN RTOUT Differential Input HIGH Voltage Differential Input LOW Voltage Differential Input Voltage (VIHD - VILD) Input HIGH Current Input LOW Current 1100 GND 100 -150 -150 40 5 VCC VIHD - 100 1200 +150 +150 mV mV mV mA mA
TERMINATION RESISTORS Internal Input Termination Resistor Internal Output Termination Resistor 45 45 50 50 55 55 W W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. CML outputs loaded with 50 W to VCC for proper operation. 6. Input and output parameters vary 1:1 with VCC. 7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single-ended mode. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
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NB7L1008M
Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V; GND = 0V TA = -40C to 85C (Note 10)
Symbol fDATA fINCLK VOUTPP Characteristic Maximum Operating Input Data Rate Maximum Input Clock Frequency, VOUTPP w 200 mV Output Voltage Amplitude (see Figures 2 and 5, Note 11) fin v 4 GHz fin v 6 GHz Input Common Mode Range (Differential Configuration, Note 12, Figure 9) Propagation Delay to Output Differential, IN/IN to Qn/Qn Propagation Delay Temperature Coefficient -40C to +85C Output Clock Duty Cycle fin v 6 GHz Duty Cycle Skew (Note 13) Within Device Skew (Note 14) Device to Device Skew (Note 15) Clock Jitter RMS, 1000 Cycles (Note 16) fin v 6 GHz Data Dependent Jitter (DDJ) (Note 17) v10 Gb/s Input Voltage Swing (Differential Configuration) (Note 18) (Figure 5) Output Rise/Fall Times (20% - 80%) Qn, Qn 100 20 45 45 Min 10 6 200 200 1050 100 160 35 49/51 0.15 7 25 0.2 3 55 1 25 70 0.8 20 1200 70 Typ 12 8 400 350 VCC - 50 250 Max Unit Gb/s GHz mV
VCMR tPLH, tPHL tPLH TC tDC tSKEW
mV ps fs/C % ps
tJITTER VINPP tr, tf
ps mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Measured using a 400 mV source, 50% duty cycle 1 GHz clock source. All outputs must be loaded with external 50 W to VCC. Input edge rates 40 ps (20% - 80%). 11. Output voltage swing is a single-ended measurement operating in differential mode. 12. VCMR min varies 1:1 with GND, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 13. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+ @ 1 GHz. 14. Within device skew compares coincident edges. 15. Device to device skew is measured between outputs under identical transition 16. Additive CLOCK jitter with 50% duty cycle clock signal. 17. Additive Peak-to-Peak jitter with input NRZ data at PRBS23. 18. Input voltage swing is a single-ended measurement operating in differential mode. 500 OUTPUT VOLTAGE AMPLITUDE (mV) 450 Q Output Amplitude (mV) 400 IN 350 300 250 200 VT 50 W IN 50 W . VCC
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Figure 3. Input Structure
fout, CLOCK OUTPUT FREQUENCY (GHz)
Figure 2. Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typical)
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NB7L1008M
IN IN Q Q tPLH VOUTPP = VOH(Q) - VOL(Q) tPHL VINPP = VIH(IN) - VIL(IN)
IN IN
VID = |VIHD(IN) - VILD(IN)| VIHD VILD
Figure 4. Differential Inputs Driven Differentially
Figure 5. AC Reference Measurement
VIH Vth VIL Vth
IN
IN
IN
IN
Figure 6. Differential Input Driven Single-Ended
Figure 7. Differential Inputs Driven Differentially
VCC Vthmax
VIHmax VILmax VIH Vth VIL VIHmin VILmin
VCC VCMmax IN VCMR IN VCMmin GND
VIHDmax VILDmax VID = VIHD - VILD VIHDtyp VILDtyp VIHDmin VILDmin
Vth
IN Vthmin GND
Figure 8. Vth Diagram
Figure 9. VCMR Diagram
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NB7L1008M
VCC
50 W Q Driver Device Q Zo = 50 W Zo = 50 W
50 W D Receiver Device D
Figure 10. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8173/D)
NB7L1008M VCCO VCC (Receiver)
50 W
50 W
Q Q
50 W
50 W
16 mA GND
Figure 11. Typical CML Output Structure and Termination
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NB7L1008M
VCC VCC VCC VCC
ZO = 50 W LVPECL Driver VT = VCC - 2 V ZO = 50 W
NB7L1008M IN 50 W 50 W IN LVDS Driver
ZO = 50 W VT = Open ZO = 50 W
NB7L1008M IN 50 W 50 W IN
GND
GND
GND
GND
Figure 12. LVPECL Interface
Figure 13. LVDS Interface
VCC
VCC
VCC
VCC
ZO = 50 W CML Driver VT = VCC ZO = 50 W
NB7L1008M IN 50 W 50 W IN Differential Driver ZO = 50 W VT = VREFAC* ZO = 50 W
NB7L1008M IN 50 W 50 W IN
GND
GND
GND
Figure 14. Standard 50 W Load CML Interface
Figure 15. Capacitor-Coupled Differential Interface (VT Connected to VREFAC)
GND
*VREFAC bypassed to ground with a 0.01 mF capacitor
VCC
VCC
ZO = 50 W Differential Driver VT = VREFAC*
NB7L1008M IN 50 W 50 W IN
GND
Figure 16. Capacitor-Coupled Single-Ended Interface (VT Connected to VREFAC)
GND
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NB7L1008M
ORDERING INFORMATION
Device NB7L1008MMNG NB7L1008MMNR4G Package QFN32 (Pb-Free) QFN32 (Pb-Free) Shipping 74 Units / Rail 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB7L1008M
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P CASE 488AM-01 ISSUE O
D
A B
2X 2X
0.15 C 0.15 C 0.10 C
32 X
0.08 C L
32 X 9 8
32 X b 0.10 C A B
0.05 C BOTTOM VIEW 0.28
32 X 28 X
GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EE EE
TOP VIEW SIDE VIEW D2
16 17 1 32 25
PIN ONE LOCATION
E
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 --- --- 0.300 0.400 0.500
(A3) A A1 C
EXPOSED PAD SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
SOLDERING FOOTPRINT*
5.30 3.20
K
32 X
E2
24
0.63
32 X
e
3.20
5.30
0.50 PITCH
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NB7L1008M/D

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